In recent years, digitization of video signal processing has been advanced, and a semiconductor device which performs video signal processing using a clock synchronized with a reference signal such as a horizontal sync signal has been utilized. As an example, there is a semiconductor device disclosed in Japanese Published Patent Application No. 2002-290218.
FIG. 21 shows a configuration example of such conventional semiconductor device.
A conventional semiconductor device shown in FIG. 21(a) includes a clock input terminal 101, delay cells 102 to 105, a phase comparator 106, a controller 107, a reference signal input terminal 108, a selector 109, and a sync clock output terminal 110.
The delay cells 102 to 105 shift the phase of a clock inputted to the clock input terminal 101, each by 1/4 clock.
The phase comparator 106 compares the phase of a clock that is one clock after the input clock with the phase of the output clock of the delay cell 105.
The controller 107 controls the delay values of the delay cells 102 to 105 on the basis of the output of the phase comparator 106.
The selector 109 selects, as a sync clock, a clock whose phase is closest to the phase of the reference signal inputted to the reference signal input terminal 108 from among the clocks outputted from the respective delay cells 102 to 105, and outputs the sync clock through the sync clock output terminal 110 to the outside.
A description will be given of the operation of the conventional semiconductor device constructed as described above, with reference to FIG. 21(b).
A clock inputted to the clock input terminal 101 is delayed by the four stages of delay cells 102 to 105. Then, in the phase comparator 106, the phase of a clock that is one clock after the clock inputted to the clock input terminal 101 is compared with the phase of the clock outputted from the delay cell 105, and the delay values of the respective delay cells 102 to 105 are controlled by the controller 107 on the basis of a phase difference that is detected as a result of the comparison.
The selector 109 selects an edge clock which is a rear part of the reference signal and is closest to the phase of the reference signal, from among the delay clocks outputted from the respective delay cells 102 to 105. In this example, the clock outputted from the delay cell 103 is selected as a sync clock, and the sync signal is outputted through the sync clock output terminal 110.